module fifo_syn_flag(clk,
                     rst,
                     wr_en,
                     rd_en,
                     empty,
                     full);
  input clk,rst,wr_en,rd_en;
  output empty,full;
  wire clk,rst,wr_en,rd_en;
  reg [5:0]fifo_cnt;
  wire empty,full;
  
  parameter RAM_MN=62;
  reg empty_in,full_in;
  assign empty=empty_in;
  assign full=full_in;
   
  always@(posedge clk or rst or wr_en or rd_en or full or empty)
    begin
      if(!rst)
         begin
           fifo_cnt=0;
           empty_in=1;
           full_in=0;         
         end
      else
        begin
          if(wr_en)
             begin
               if(rd_en)
                  begin
                    fifo_cnt=fifo_cnt;
                  end
               else
                  begin
                    if(!full)
                      begin
                        fifo_cnt=fifo_cnt+1;
                        empty_in=0;
                        if(fifo_cnt==RAM_MN)
                           full_in=1;                           
                      end
                  end
             end
          else
            begin   
              if(rd_en)
                begin
                  if(!empty)
                    begin
                      fifo_cnt<=fifo_cnt-1;
                      full_in=0;
                      if(fifo_cnt==0)
                        empty_in=1;
                    end
                end 
               else
                 fifo_cnt<=fifo_cnt;       
            end
        end       
    end
endmodule